| 摘要 |
A differential switched capacitor circuit (6) for sampling a differential input signal (IP, IM) in different sampling phases (PHI0, PHI1) and for correcting errors at an output thereof, comprises: m switched capacitor stages (8-16) coupled in a chain, a first stage (8) being coupled to the output of the circuit, each of the m switched capacitor stages (8-16) being coupled to an adjacent stage in the chain depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain and wherein the mth stage (16) is selectively coupled to an end node so as to cancel the charge thereon, whereby after a number of sampling phases the error at the output is substantially reduced by a factor of up to 1/m.
|
