Sequential parity correction for error-correcting RAM array

摘要

An apparatus and method of correcting parity errors in a fault tolerant computer system. Data and associated parity are checked in parallel with use of the data by an ALU. Upon detection of an error, a controller causes the ALU to pass the input data unchanged and associates a correct parity with the input data. The correct parity generation is done in parallel with ALU processing to permit rapid reassociation of data and its correct parity. The reassociated data is returned to the ALU for processing.