发明名称 DELAY LOCKING SIGNAL PROCESSING CIRCUIT AND THE METHOD THEREFOR
摘要 The method comprises the steps of setting a V. T. R system; checking which mode the system is on a still mode or a slow mode; if it is not a still mode and if a still key is input, setting an output of the still mode; converting a value by generating a control signal for still switching and checking if the still vertical buffer is set; if a slow key is input, setting a slow mode flack and a slow interval time; if the slow mode is input and the interval time is last, returning to the step of setting the slow interval time; and checking the state of the still performance buffer by setting the slow mode flack at a state "0", if there is a slow release key.
申请公布号 KR960005944(B1) 申请公布日期 1996.05.03
申请号 KR19890009091 申请日期 1989.06.29
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 YU, JAE - CHUN
分类号 H04N5/783;(IPC1-7):H04N5/783 主分类号 H04N5/783
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