| 摘要 |
A bus structure for sensitive analog signals suitable for testability in integrated circuits. The structure incorporates one or more simple 3-state inverters each having a first input for receiving test data from a node of interest and a second input selectively supplied with an enabling signal to initiate a test mode. The output of the 3-state inverter is connected to an operational amplifier circuit via a common analog bus. The operational amplifier circuit maintains the bus at a substantially constant voltage. The output voltage of the operational amplifier will be approximately linearly proportional to the test data. |
