Bus locking mechanism in a computer system

摘要

A bus locking mechanism is provided in a computer system having a central processing unit connected to a memory controller, a memory connected to the memory controller via a memory bus and a peripheral interface connected to the memory controller via an input-output bus. The locking mechanism preferably uses the processor's N_RSRV output signal to detect the state of the central processor's internal reservation coherency bit. When this bit is set, the memory controller locks the memory and input-output busses for the exclusive use of the central processor. This bus locking prevents a bus mastering peripheral device from interrupting the processor while the processor is performing a Read/Modify/Write instruction. <IMAGE>