发明名称 Image decoding apparatus
摘要 <p>Encoding data are given to a variable-length decoding circuit and are decoded, and are given to a memory so as to be stored therein. The same data are read out from the memory, whereby decoding processing of the encoding data is executed twice within one frame period. Decoding data due to the twice decoding processings are stored in the memory at an output part thereof. Data of odd fields are read out in display order in the first half of the display period of one frame. Data of even fields are read out in display order in the latter half of the display period of one frame. Thus, even in case where restored image data of a B-picture are outputted in interlacing, a memory capacity can be reduced. <IMAGE></p>
申请公布号 EP0710028(A2) 申请公布日期 1996.05.01
申请号 EP19950307609 申请日期 1995.10.25
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOUICHI, KURIHARA;SHUJI, ABE, KUREALE
分类号 G06T9/00;H04N7/26;H04N7/46;H04N7/50;(IPC1-7):H04N7/24 主分类号 G06T9/00
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