Process for testing integrated circuits with at least one logic circuit and testable integrated circuit

摘要

PCT No. PCT/DE92/00638 Sec. 371 Date May 26, 1994 Sec. 102(e) Date May 26, 1994 PCT Filed Aug. 3, 1992 PCT Pub. No. WO93/03434 PCT Pub. Date Feb. 18, 1993.For real-time testing, two test combinations TK1 and TK2 are written to the input trigger circuits (EK1 to EK2) of the logic circuit (LS1) to be tested and to the output trigger circuits (AP1 to AP2) of the upstream test device (TE) or of an upstream logic circuit (LSO). The second test combination TK2 is transferred with the first system test pulse to the input trigger circuits (EK1 to EK3), and with the second test pulse the associated output combination (AT2) is transferred into the output trigger circuits (AK1 to AK2). This output combination is subsequently transferred into the test device (E) and checked. An integrated circuit suitable for carrying out the process has trigger circuits with two clock inputs.