发明名称 PARALLEL COMPUTER SYSTEM
摘要 PURPOSE: To provide a technology to attain a network control which is excellent in its cost performance and contains many functions in a multiprocessor computer system that is connected to a network. CONSTITUTION: In computer system where processors A to D are mutually connected via a network 105, an interruption signal line is added to an additional transmission line. A packet is used for communication of processors A to D, and a barrier synchronizing packet of the fixed length is used for the barrier synchronizing processing. The barrier synchronizing packet is transferred from a transmission control circuit via the same transmission line as a normal packet. Furthermore, an interruption signal is sent to the interruption signal line. On the other hand, a reception control circuit is provided with a priority control circuit that decides the highest priority for the barrier synchronizing packet. Thus, the reception control circuit sends the barrier synchronizing packet to each processor in response to the interruption signal sent to the interruption signal line and without writing the barrier synchronizing packet into a register that is prepared for storage of the normal packet.
申请公布号 JPH08110894(A) 申请公布日期 1996.04.30
申请号 JP19950205804 申请日期 1995.08.11
申请人 HITACHI LTD 发明人 NAKAGAWA TAKAYUKI
分类号 G06F15/17;G06F9/52;G06F15/16;G06F15/177 主分类号 G06F15/17
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