Non-scan design-for-testability of RT-level data paths

摘要

Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.