PACKET PHASE SYNCHRONIZING CIRCUIT

摘要

PURPOSE: To reduce the capacity of a memory to be used for a phase synchronization and to reduce the delay due to phase synchronization by performing the phase synchronization for every packet and reading the packets from a buffer memory. CONSTITUTION: The packets included in an input transmission signal are successively written in an FIFO 101. This siting control is performed by detecting the location of an input packet and transmitting a siting clock to the FIFO 101 only while the packet arrives by the information showing a frame signal F, a transmission line clock CK1 and the head location of the payload area in the input transmission signal and the location of the space area, by a writing control circuit 102. The packet reading control from the FIFO 101 is performed by preparing a reading clock by a station clock CK2 for synchronization and a start signal and transmitting the clock to the FIFO 101.