发明名称 Multilayer package with second layer via test connections
摘要 A package is disclosed that incorporates recessed test vias into a circuit substrate. The test vias are preferably formed at the time of substrate manufacture with little additional cost and offer access to electrical test points after hermetic sealing of the package without competing for lead sites on an otherwise crowded package exterior. The vias are preferably recessed below the surface of the substrate and may be backfilled with insulation to prevent unintended contact. Alternatively, the vias may be incorporated into the side of a package used for mounting to a motherboard, in which case the vias will be sealed at the time of package mounting. In still another instances, the vias may be left accessible or filled with a material that is easily removed for later test and service.
申请公布号 US5512710(A) 申请公布日期 1996.04.30
申请号 US19920934068 申请日期 1992.08.21
申请人 CTS CORPORATION 发明人 SCHROEDER, DONALD R.
分类号 G01R31/28;H01L23/58;(IPC1-7):H01L23/02 主分类号 G01R31/28
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