Control channel interface circuit

摘要

A group of control time slots of each system frame is reserved for the passage of control messages between a call processor and a control channel interface circuit. Each of the latter monitors the system bus and removes address information from the bus during time slot zero. Microprocessor control information that is to be sent up-link to a call processor is stored in a control channel interface circuit output buffer. Upon being polled by a call processor, each control channel interface circuit of the group polled and having up-link information responds to the call processor by transmitting a one bit reply during the succeeding time slot two.