| 摘要 |
A signal (LOCK-ALARM) of a locking detector of a synthesizer indicates in a first state that a loop is locked, and in a second state that the loop is unlocked. The synthesizer may be temporarily deactivated by switching off the operating voltage of a voltage controlled oscillator by means of a switching signal (CNTRL). The alarm circuit of the synthesizer of the invention comprises a first detector (1), the state of the output of which changes with a delay, in response to the change of the signal (LOCK-ALARM) of the detector conveyed to said detector, and a second detector (2), the state of the output of which changes with a delay, in response to the change of the switching signal (CNTRL) conveyed to said detector, and a device (3) generating the alarm signal, said device providing the output signal (SYNTE-ALARM) of the alarm circuit in response to the output signals of the detectors. By selecting appropriate delay-times for the detector, it is possible to achieve the intended operation.
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