| 摘要 |
PCT No. PCT/SE95/01215 Sec. 371 Date Jul. 9, 1997 Sec. 102(e) Date Jul. 9, 1997 PCT Filed Oct. 17, 1995 PCT Pub. No. WO96/12230 PCT Pub. Date Apr. 25, 1996The present invention relates to a system for processing of memory data in the form of stored variables. The system comprises at least one data execution unit (IPU), a common data memory (DS), a central processor bus and a function unit (30) for autonomous handling of variables. Each variable has a logical address or a base address and the function unit (30) comprises means for converting logical addresses to physical addresses. The function unit further comprises first memory means (1) for storing calculated physical memory addresses and second memory means for temporary storing of the last calculated address temporarily and in sequence. In the function unit (30), a comparing arrangement (JMF) is arranged for comparing the addresses of incoming memory requests with physical word addresses for particularly the last requested memory address (A4). When the addresses are the same (A3-A4), memory data of the first requested memory address is reused. |
