发明名称 |
COHERENCY AND SYNCHRONIZATION MECHANISM FOR I/O CHANNEL CONTROLLERS IN A DATA PROCESSING SYSTEM |
摘要 |
An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity. |
申请公布号 |
WO9611430(A2) |
申请公布日期 |
1996.04.18 |
申请号 |
WO1995IB00910 |
申请日期 |
1995.09.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM DEUTSCHLAND GMBH |
发明人 |
ARIMILLI, RAVI, K.;DODSON, JOHN, S.;GUTHRIE, GUY;LEWIS, JERRY, D. |
分类号 |
G06F12/08;G06F13/12;G06F13/28;G06F13/40;G06F15/16;G06F15/177 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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