Self test mechanism for embedded memory arrays.

摘要

A method and mechanism for testing an embedded array is shown. The mechanism includes a deterministic test pattern generator which transmits test patterns to the array. The patterns are preselected based on the failure propensities of the array. The contents of the array are read and compared to the test pattern to generate a current error term. The current error term is compressed in a register through a logical operation which preserves an error indication. The contents of the register constitute a cumulative error term, and may be read to determine if an error has occurred. Each column of the tested array corresponds to a bit position in the cumulative error term, whereby a user may determine which column in the array causes an error.