发明名称 Display mode detector, pixel clock synchroniser and interpolator for ferroelectric liquid crystal display
摘要 <p>A display control apparatus for displaying an image by receiving an RGB video signal including an image signal and a synchronizing signal receives horizontal and vertical synchronizing signals in the RGB video signal, and detects the current display mode using a display mode detector. A pixel synchronizing clock signal is generated using a clock generator in correspondence with the detected display mode, and the RGB video signal is interpolated by an interpolation processing circuit in correspondence with the display mode and the display screen size of an FLCD panel. The interpolated video signal is subjected to image signal processing, and the processed video signal is displayed on the FLCD panel. &lt;IMAGE&gt;</p>
申请公布号 EP0707305(A2) 申请公布日期 1996.04.17
申请号 EP19950116047 申请日期 1995.10.11
申请人 CANON KABUSHIKI KAISHA 发明人 SAWADA, MASAYUKI,
分类号 G02F1/133;G06T3/40;G09G3/20;G09G3/36;G09G5/00;G09G5/18;H03L7/099;H03L7/10;(IPC1-7):G09G3/36 主分类号 G02F1/133
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