| 摘要 |
PURPOSE: To reduce the circuit scales of a collation part and a collation deciding part and to decrease the number of parts by constructing each part of a frame synchronization pattern consisting of 48 bits, for example, so that the component parts of this pattern can be collated with each other in sequence and in several times. CONSTITUTION: The data inputted from a transmission line are defined as a 1.5M logical bus termination part and turned into a 1.5M logical bus frame level through multiple separation. Then an S1-bit extracting part 1 of frames is inputted to a shift register 2 consisting of 64 stages. A frame synchronization pattern consists of 48 bits, and conventional 384 bits are treated in sequence and in several times. That is, the frame synchronization patterns included in a 1.5M logical bus frame undergo the sequential collation every 8 bits. Then the synchronization pattern is taken out together with a collation pattern stored in a memory. These two patterns are compared with each other, and 6 different ways of the pattern consisting of 48 bits are stored in the memory. When the first 8 bits of the pattern are coincident with one of collation patterns stored in the memory, the result of collation is outputted to a synchronization deciding part 6. Then the following collation of patterns are carried out in sequence. |
