LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY

摘要

PURPOSE: To provide the layout of a redundancy circuit, wherein the chip area required for realization of redundancy becomes a minimum area. CONSTITUTION: An array MAR of a programmable nonvolatile memory, which stores a redundancy bit line, a redundancy word line, a defective bit line, which should be functionally replaced respectively, and the address of a word line is provided. The layout of the redundancy circuit is divided into a plurality of the same layout strips LS1-LS4, which intersect the array at right angles and have first and second strip parts at both sides of the array. The first strip part intersects a column-address signal bus CABUS, extending in parallel with the array. The second strip part intersects a row-address signal bus (RABUS), extending in parallel with the array.