| 摘要 |
<p>PURPOSE: To attain a high processing speed and to reduce the circuit scale. CONSTITUTION: Eight signals are given from an input terminal to an addition/ subtraction arithmetic circuit 3 in a horizontal direction, from which an addition signal string and a subtraction signal string are obtained, they are fed respectively to product sum arithmetic circuits 4, 5, in which product sum arithmetic processing is conducted in 2 and 4 cycles respectively. An arithmetic outputs obtained by multiplying one arithmetic output and other arithmetic output by a coefficient by a weighting circuit 6 are subjected to transposing processing by a transposition circuit 7 and the presence of motion is detected in a motion detection circuit 8. When no motion exists, the output is fed from a branch path 201 to the product sum arithmetic circuit 4, in which the data are processed similarly. When motion exists the data are fed from a branch path 202 to the arithmetic circuit 3, and its arithmetic output is subjected to product sum arithmetic processing in the product sum arithmetic circuit 4. Each DCT coefficient is outputted to an output terminal 2. Thus, each circuit uses in common DCT, IDCT and processing with/without motion.</p> |
