| 摘要 |
<p>PURPOSE: To speed up processing and decrease the circuit scale. CONSTITUTION: Eight signals are inputted horizontally from an input terminal to a sum and difference arithmetic circuit 3 to obtain an addition signal sequence and a subtraction signal sequence, which are applied to product sum arithmetic circuits 4 and 5 respectively, so that product sum arithmetic processes are performed in two cycles and four cycles respectively. After one arithmetic output and the arithmetic output obtained by multiplying the other arithmetic output by a coefficient through a weighting circuit 6 are transposed by a transposing circuit 7, a motion detecting circuit 8 detects whether or not there is motion. When there is no motion, the output is applied from a branch path 201 to the product sum arithmetic circuit 4 and then processed similarly. When there is the motion, on the other hand, the output is applied from the branch path 202 to the sum and difference arithmetic circuits 3, whose arithmetic outputs are supplied to the product sum arithmetic circuits 4 to perform product sum operations respectively. Respective DCT coefficients are outputted to output terminals 2. Consequently, those circuits can share DCT and IDCT.</p> |
