发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PURPOSE: To eliminate a gate offset region on the side of a source and reduce on-resistance of a transistor by a method wherein a thin film region of a gate oxide film forming a heavily doped source and drain layer is self-alizningly formed for a gate electrode of a high breakdown strength MOS transistor. CONSTITUTION: A gate electrode 26B of a normal breakdown strength MOS transistor is formed on a thin gate oxide film 24 and a gate electrode 26A of a high breakdown strength MOS transistor is formed on a thick gate oxide film 22. With the use of these gate electrodes 26A, 26B as a mask, gate oxide films 24, 25 are dry-etched up to substantially 300Åor less. Thereafter,<31> P<+> ions are ion-implanted on one side of the gate electrode 26A, whereby a lightly doped drain layer 28 is formed. Next<75> As<+> ions are ion-implanted, whereby heavily doped source and drain layers 30, 31 of a normal breakdown strength MOS transistor and heavily doped source and drain layers 32, 33 of a high breakdown strength MOS transistor are formed.
申请公布号 JPH08102496(A) 申请公布日期 1996.04.16
申请号 JP19940237479 申请日期 1994.09.30
申请人 SANYO ELECTRIC CO LTD 发明人 KIKUCHI SHUICHI;WATANABE YUICHI;MITSUSAKA EIICHI;TSUKADA YUJI
分类号 H01L29/78;H01L21/8234;H01L27/088;(IPC1-7):H01L21/823 主分类号 H01L29/78
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