| 摘要 |
PURPOSE: To obtain a PLL synthesizer device capable of reducing the generation of noises due to the switching timing of charge pumps. CONSTITUTION: A delay circuit 5 is connected to the prestage of one phase comparator 2b out of two phase comparators 2a, 2b in the PLL synthesizer circuit and the switching timing of charge pumps 3a, 3b is shifted from each other, so that the generation of a noise due to the switching of the charge pumps 3a, 3b can be reduced. |
