| 摘要 |
<p>PURPOSE: To reduce the threshold value voltage distribution and to improve the yield without increasing routine operation and erase time by executing and initializing prescribed three routines. CONSTITUTION: Erase unit memory cells of floating gate FETs M00 , M01 ... and M10 , M11 , etc., of which sources of a memory cell array 1 are common, are initialized by the execution of three routines 101-103 of excess erase, write return and threshold value voltage upper limit value checks through write/erase sequence control circuit and voltage supply circuit 9 based on a command from a control terminal CTR. In the routine 101, until the excess erase and erase verification of which threshold value voltages become prescribed values, and in the routine 102, until the threshold value voltage becomes a lower limit value or above, the write return and verification are repeated, and in the routine 103, the verification verifying that a threshold value upper limit voltage is the prescribed value or below is repeated. Thus, the initialization with the reduced threshold value voltage distribution is attained without increasing the routine operation and the erase time, and the yield is enhanced.</p> |
