| 摘要 |
An efficient method for manufacturing a fork-shaped capacitor, for use as part of a DRAM cell, is described. Starting with a partially completed silicon integrated circuit, comprising a plurality of Field Effect Transistors, the electrode contacting the gate region is given the shape of a hollow rectangle. One side contacts the gate region while the parallel side is on a layer of field oxide, adjacent to it and separated from it by the source region. The structure is then coated with a first layer of silicon oxide which is then selectively removed so as not to cover the interior of the gate electrode. Then the structure is coated with a first layer of doped polysilicon and with a second layer of silicon oxide, the part that overlies the interior of the gate being then selectively removed. The entire structure is now conformally coated with a third layer of silicon oxide which is then etched back down to the level of the first polysilicon layer, leaving the second layer of silicon oxide substantially unaltered. Thus, spacers are formed that extend inwards from the vertical walls of said second layer of silicon oxide, partially covering the exposed portion of the first layer of polysilicon. The latter is then etched, down to the level of the upper surface of the gate electrode, and the second layer of silicon oxide, including the spacers, is then removed. Next, all of the first layer of polysilicon is removed, except the part that overlies the gate interior and overlaps the first layer of silicon oxide. The first layer of polysilicon is now ready to serve as a bottom electrode for the capacitor which is completed by depositing a dielectric layer and a top electrode layer.
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