发明名称 |
Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through |
摘要 |
An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
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申请公布号 |
US5508957(A) |
申请公布日期 |
1996.04.16 |
申请号 |
US19940312072 |
申请日期 |
1994.09.26 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MOMODOMI, MASAKI;MASUOKA, FUJIO;ITOH, YASUO;IWAHASHI, HIROSHI;IWATA, YOSHIHISA;CHIBA, MASAHIKO;INOUE, SATOSHI;SHIROTA, RIICHIRO;NAKAYAMA, RYOZO;OHUCHI, KAZUNORI;WATANABE, SHIGEYOSHI;KIRISAWA, RYOUHEI |
分类号 |
G11C16/04;G11C16/10;G11C16/16;G11C16/30;H01L27/115;(IPC1-7):G11C16/04;G11C16/06;H01L29/788 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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