发明名称 OUTPUT BUFFER CIRCUIT
摘要 PURPOSE: To obtain an output buffer circuit in which a rise time or a fall time of an output voltage at an output terminal is decreased and transfer delay time of an output voltage is minimized. CONSTITUTION: A capacitive means including a gate electrode capacitance of an output drive MOS transistor(TR) is gradually charged to make a rise time or a fall time short in the output buffer circuit and the output buffer circuit is provided with threshold voltage charge means 1, 2 charging quickly the capacitive means up to a threshold voltage of the output drive MOS TR.
申请公布号 JPH0897700(A) 申请公布日期 1996.04.12
申请号 JP19940235151 申请日期 1994.09.29
申请人 NEC CORP 发明人 ONISHI YASUHIRO
分类号 H03K19/003;H03K4/00;H03K17/04;H03K17/16;H03K17/687;H03K19/017;H03K19/0175 主分类号 H03K19/003
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