LSI WITH BUILT-IN CLOCK GENERATOR/CONTROLLER OPERATING WITH LOW POWER CONSUMPTION

摘要

PURPOSE: To suppress the skew that occurs between an external system clock and an internal clock by providing a frequency phase lock loop circuit which secures the synchronization of phases between the actual external system clock and the internal clock. CONSTITUTION: An external system clock is received by a signal input terminal 207, and a phase comparator 211 compares the phase of the external system clock received from the terminal 207 with that of an internal clock which is divided by a divider 210. The result of this comparison is converted into the analog voltage by an LPF 212. Then, the oscillation frequency is changed by a voltage control oscillator 213 in response to the output of the LPF 212. The phase and the frequency of the output signal of the oscillator 213 are synchronized with those of the external system clock. Thereby, the skew occursing between the external system clock and the internal clock can be suppressed.