发明名称 METHOD FOR SPECIFYING TEST IMPOSSIBILITY FLAW IN LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To specify a more than ore defects contained in both first and second detect sets, as a defect impossible to test so as to efficiently specify a defect impossible to test. SOLUTION: When a circuit conductor in a given circuit is selected, the circuit conductor is marked to a logic value 0 as impossible control (hypothetically). Then, an agreement procedure is applied, and similarly, a node in another circuit so as to be set to a suitable logic value, that is, it is marked as impossible control or impossible observation. Accordingly, a first set of defects which cannot be tested is hypothetically delivered. Next, the selected circuit conductor is marked to a logic 1 (hypothetically) as impossible control. Then an agreement procedure is applied, and similarly, a second set of defects which cannot be tested is hypothetically delivered. Further, defects exhibited in both defect sets are automatically impossible in testing. Thus, a defect impossible to test delivered due to defects exhibiting in both defect sets can be specified.
申请公布号 JPH0894720(A) 申请公布日期 1996.04.12
申请号 JP19950261073 申请日期 1995.09.14
申请人 AT & T CORP 发明人 MIRON ABURAMOBUISHII;MAHESHIYU ANANTARAMAN AIYAA
分类号 G01R31/317;G01R31/3183;G01R31/3185;G06F11/22;G06F17/50 主分类号 G01R31/317
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