| 摘要 |
PURPOSE: To reduce a width of a memory cell in its word line direction and ease increasing of memory capacity by arranging first and second electric power line in parallel with first and second load transistors and first and second driving transistors in between and further arranging a pair of first and second bit lines across the first and second electric power lines. CONSTITUTION: First and second electric power lines 44 and 45 are arranged with first and second load transistors P1 and P2 and first and second driving transistors N1 and N2 in between. Therefore, only two bit lines are arranged in one memory cell in a direction crossing a word line. That is, a first Al wiring 44 and a second Al wiring 45 form an electric power line, and a drain for the transistor P1 is connected to a gate of the transistor P2 and transistor N2. In addition, a drain of the transistor P2 is connected to a gate of the transistor P1 and transistor N1. |
