| 摘要 |
PURPOSE: To turn a selection circuit and a loop back circuit to a small scale and to provide inexpensive system constitution by utilizing the relation of the byte number of a header and the bit number of delay data and performing a loop back operation in the entire shift register. CONSTITUTION: The shift registers(SRs) 7 and 9 for respectively storing 40 bits for five stages of 8-bit parallel data(PD) and 3 bits for one stage of 3-bit PD are provided. A selector 11 respectively selects and outputs the output of the fifth stage of the SR 7 to the first stage of the SR 7 at the time of header transmission(HT) and the 8-bit PD to the first stage of the SR 7 at the time of payload transmission(PT). Also, the selector 13 respectively selects and outputs the output of the SR 9 to the SR 9 at the time of the HT and 3-bit data in the output of the fifth stage of the SR 7 to the SR 9 at the time of the PT. Further, the selector 1 respectively selects and outputs unscrambled data at the time of the HT and the data scrambled by using the delay data of the SRs 7 and 9 at the time of the PT. Thus, the need of the selector and the loop back circuit for holding the data of F.F or the like is eliminated.
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