| 摘要 |
PURPOSE: To provide the circuit and method for pattern detection which can detect an optional number of data patterns. CONSTITUTION: In synchronism with a clock signal CK, input data IN7 -IN0 in serial format are inputted to an S/P converting circuit 10 and converted into address data Q7 -Q0 in parallel format, which are inputted address terminals A7 -A0 of a ROM 20. When the input data IN7 -IN0 are, for example, 00111100B, the value of the address data P7 (Q7 -Q0 ) of the S/P converting circuit 10 is 3Ch. A ROM 20 is stored with a numeral 1 only in an address 3Ch and a numeral 0 in other addresses. Therefore, output data OUT has a logical value 1 while the address data P7 is outputted from the S/P converting circuit 10 and in the period wherein the clock signal CK has a logical value 0. |
