| 摘要 |
PURPOSE: To realize a shuffle processing by memory capacity less than shuffling in conventional frame unit. CONSTITUTION: Field data written in an address on a two port field memory 2, which is designated by a write part memory designation circuit 3 and an intra partial memory write address generation circuit 4, is read out of an address designated by a read part memory designation circuit 5 and an intra- partial memory read address generation circuit 6. The write part memory designation circuit 3 and the intra-partial memory write address generation circuit 4 designate the blank address from which data is read out, and writes next field data. Field data which is read out of the two port field memory 2 is controlled to be written and read into/from a field 1 FIFO memory 7 and a field 2 FIFO memory 8 by an FIFO control circuit 9. |
