| 摘要 |
PURPOSE: To obtain a semiconductor integrated circuit capable of performing a high speed memory while reducing through current by using a first conduction type MOS transistor and a second conduction type MOS transistor connected in series between a first reference power source and a second reference power source. CONSTITUTION: An N channel type MOSFET 6 and a P channel MOSFET 7 are connected in series to each other between two reference power sources VCC and a GND and an external load capacitance CL is connected between the connection node ND of these transistors and the GND. Since a time is needed for transiting the output data DOUT of an output terminal directly from an H level to an L level or vice versa, the output is delayed. An intermediate potential setting circuit for suppressing this, in the case where the output data is set to an intermediate potential from the H level or the L level, bringes the potential of the output terminal to the direction opposite to the potential of the output data in a previous cycle. The through current is prevented from flowing in a circuit by setting the intermediate potential while making one of MOSFETs 6, 7 conductive. |
