AN INSTRUCTION LENGTH DECODER FOR VARIABLE LENGTH INSTRUCTIONS

摘要

A circuit (50) and method for supplying output length marks indictive of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer (210). A plurality of programmable logic arrays (PLAs) (222a..222p) is coupled to receive pedetermined sets of bytes from the input buffer and to provided instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry (240), which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic (260) for length calculations spanning into the next input buffer of instruction code. An FCC latch (258) latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instructing, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started.