发明名称 VARIABLE-LENGTH BIT DATA PROCESSING CIRCUIT AND METHOD
摘要 <p>A variable-length bit data processing circuit includes first, second and third one-word registers (12, 20, 22). Data from a memory is loaded to the first register (12), and variable-length bit data is taken out from the third register (22). The second and theird registers (20, 22) are coupled with a barrel shifter (16), which shifts two-words of data in accordance with barrel shift quantity data based on the number of effective bits and remaining bits obtained from a subtracter (30).</p>
申请公布号 WO1996010788(P1) 申请公布日期 1996.04.11
申请号 JP1995001959 申请日期 1995.09.27
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