| 发明名称 |
Header translation unit for an ATM switching system |
| 摘要 |
<p>An exchange termination apparatus of an asynchronous transfer mode switching system, wherein a contents addressable memory, is used to effect a mapping function between a plurality of logical addresses and a plurality of physical addresses.</p> |
| 申请公布号 |
EP0500238(B1) |
申请公布日期 |
1996.04.10 |
| 申请号 |
EP19920301016 |
申请日期 |
1992.02.06 |
| 申请人 |
ROKE MANOR RESEARCH LIMITED |
发明人 |
STEWART, IAN BERNARD |
| 分类号 |
H04L12/70;H04L12/935;(IPC1-7):H04L12/56 |
主分类号 |
H04L12/70 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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