发明名称 |
Improvements in or relating to semiconductor devices and their manufacture |
摘要 |
<p>This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop. <IMAGE></p> |
申请公布号 |
EP0706215(A2) |
申请公布日期 |
1996.04.10 |
申请号 |
EP19950114438 |
申请日期 |
1995.09.14 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
JENG, SHIN-PUU |
分类号 |
H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L23/532 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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