| 摘要 |
A sampling filter-detector receives input signals of different frequencies and provides an output, or detect signal, only when the input frequency has a predetermined value essentially equal to the drive frequency of the sampling circuit. The input signal is coupled through a series of solid state switches, or multipliers, to storage, or sampling, capacitors, the average voltages of which are coupled through voltage peak and valley followers to a comparator which supplies an output or detect signal only when the difference between the positive and negative voltage inputs to the comparator is greater than a certain value. This occurs when the input frequency is within the detector bandwidth. A threshold voltage of a desired value may be placed in the circuit coupling the peak follower and the positive input of the comparator. The solid state switches are turned on and off by pulses from digital logic means such that the switches are on 120 DEG apart in time for the drive frequency which is equal to the frequency to be detected by the filter detector. The response to the third harmonic of the input signal fundamental is eliminated as are multiples of the third harmonic.
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