发明名称 |
Method for minimizing the time skew of electrical signals in very large scale integrated circuits |
摘要 |
A method for minimizing the time skew between signals traveling through various multi-cycle path nets linking one or several VLSI packages that includes a plurality of IC chips interconnected to each other. The method includes equalizing differences between the early and the late mode slack for each of the multi-cycle nets to decrease the joint probability of failure; maximizing the time balance between the early and the late mode slack; balancing over all the nets the difference between the early and the late mode slack, minimizing in the process statistical variations within the mode slack pair; and compensating for asymmetries between rising and falling switching times using the mode slack pair. The method allows multi-cycle path nets have their transmission line length confined between a maximum and a minimum length, which in turn minimizes the skew between signals in each of the nets, decreases cycle time and .improves the overall performance of the system.
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申请公布号 |
US5507029(A) |
申请公布日期 |
1996.04.09 |
申请号 |
US19950371329 |
申请日期 |
1995.01.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GRANATO, MICHAEL A.;MICELI, GREGORY F.;RELIS, JEROME R.;SELINGER, CRAIG R.;WATTS, VERNON L. |
分类号 |
F02B75/02;G06F1/10;G06F17/50;(IPC1-7):G06F15/60 |
主分类号 |
F02B75/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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