| 摘要 |
A pipeline processor having a hardware loop function, and having transfer paths L14 and L13 which directly transfer a value of a flag register 10 being set according to the results of the operations to a loop control unit 11, and so configured that the loop control unit 11 reads the value of the flag register 10 via the transfer paths L14 and L13 and terminates a loop processing when it is the predetermined value. The loop processing can be terminated without adversely affecting the data processing efficiency when a conditional jump instruction is executed during the loop processing, and operations, data transfers and other processings can be executed other than a loop-escaping operation.
|
