| 摘要 |
An asynchronously concurrent matrix macroprocessor that consists of a substrate on which is carried an extended set of parallel-wired buses. An indefinitely large multi-dimensional rectangular array of substantially identical large scale integrated solid-state electronic modules each containing a plurality of ALUs are mounted on the substrate and communicate with each other via said extended set of parallel wired buses. The modules are located at the intersection nodes of said rectangular array with the set of parallel wired buses constituting congruent data and address buses. A control generates a unique location address for each node in the array, and a unique identifying address for each segment of external input data. A switch is contained in each module located at each node in the array for interconnecting data and address buses to route the information from a source node in the array to a target node. A static random access memory is included in each module for containing intermediate results and status information corresponding to each original input-identification address and to issue a target node address, based on the original input-identification address, for chaining modules together into preselected data flow itineraries, to perform a sequence of functional ALU operations to develop external output data from original input data so that multiple data streams can intermingle concurrently.
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