| 摘要 |
A pipeline processor 2 having an associated branch cache 4 is provided. Each cache line 12 of the branch cache stores a cache TAG, a next branch data value R, a target address value TA and a target instruction value TI. The next branch data value indicates when the next branch instruction will be encountered in the stream of instructions fed to the pipeline processor. This data is used such that following a branch cache hit, no further reading of the branch cache is made until the next branch data indicates that the next branch instruction should have been reached. At this stage, the branch cache 4 is read to see if it contains corresponding data for that next branch instruction that will avoid the need to decode that next branch instruction before instructions from the target address of that branch instruction can be fed into the pipeline. The avoiding of the need to read the branch cache for every instruction fed into the pipeline saves power.
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