| 摘要 |
A line impedance synthesis circuit for a telecommunication line circuit is described which is coupled to line terminals (AW,BW) of a telecommunication line and fed from first (GND) and second (VBAT) terminals of a voltage supply source. The line terminals (AW,BW) are coupled to these supply terminals via respective first and second impedance means which include a main path (A-B) of a first transistor circuit (K1A/K1B) shunted by the series connection of a resistance circuit (TRA/TRB) and a main path (A-B) of a second transistor circuit (K2A/K2B), control electrodes (CT) of the first (K1A/K1B) and second (K2A/K2B) transistor circuits being coupled to a same control output of a control circuit (AMPA,SUMA/AMPB,SUMB). <IMAGE> |
