发明名称 |
COMBINED PROGRAMMABLE LOGIC ARRAY AND ARRAY LOGIC |
摘要 |
A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.
|
申请公布号 |
WO9610295(A1) |
申请公布日期 |
1996.04.04 |
申请号 |
WO1995IB00716 |
申请日期 |
1995.08.30 |
申请人 |
PHILIPS ELECTRONICS N.V.;PHILIPS NORDEN AB |
发明人 |
CLINE, RONALD, LEE |
分类号 |
H03K19/173;H03K19/177;(IPC1-7):H03K19/177 |
主分类号 |
H03K19/173 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|