COMBINED PROGRAMMABLE LOGIC ARRAY AND ARRAY LOGIC

摘要

A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.