| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a redundant execution circuit minimizing a chip area and minimizing the number of test routes connected by mounting a comparator comparing a specific memory cell and an address bit, a switch connected to a reductant address line, etc. SOLUTION: An address pad 20 for receiving an address bit is Joined with an address buffer 22, and an output from the address buffer 22 is connected to a redundant address line driver 24. The redundant address line driver 24 is controlled by the complementary signals READ and inverse READ of separately set lines 26 and 28 in the normal operation of a chip and the redundant address line driver 24 is turned on. An output test line driver 30 is supplied with the signals READ and inverse READ of the lines 26 and 28 in reverse relationship, and the output test line driver 30 is turned off when the redundant address line driver 24 is turned on and reverse relationship is acquired.</p> |
