| 摘要 |
An address information reading-out apparatus of an FDDI network system for transmitting a packet composed of a plurality of m-bit symbols includes an m-bit data bus, an nxm-bit data bus, a control signal generator for detecting start and control symbols among the plurality of symbols received via said m-bit data bus and generating control signals, an input latch for alternately latching the address symbols having an odd number and the address symbols having an even number among the plurality of symbols, in response to the control signal of the control signal generator, an output latch for latching a pair of address symbols from the input latch in response to the control signal of the control signal generator and outputting onto the nxm-bit data bus, and a content addressable memory for receiving the address symbol from the nxm-bit data bus in response to the control signal of the control signal generator, determining whether the input symbol matches predetermined address information, and if so, generating a reading-out signal. Therefore, address information can be read out by hardware, thereby reducing the load on the CPU of the system and improving the performance of the system.
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