| 摘要 |
PURPOSE: To provide a phase locked loop circuit which realizes quick synchronization and the stable steady state in the case of the use of a lag/lead filter as well as the use of a lag filter by including no harmonic components in the output signal from a voltage controlled oscillator. CONSTITUTION: A first multiplier 1-1 multiplies an input signal and the output signal of the voltage controlled oscillator. A second multiplier 1-2 multiplies the signal, which is obtained by shifting the input signal in a first phase shifter 1-6 by 90 deg., and the signal obtained by shifting the output signal of the voltage controlled oscillator 1-5 in a second phase shifter 1-7 by 90 deg.. An adder 1-3 adds the multiplication result of the first multiplier 1-1 and that of the second multiplier 1-2. Consequently, only the signal of the frequency difference between the input signal and the output signal of the voltage controlled oscillator 1-5 appears as the addition result of the adder 1-3, and a harmonic signal is not outputted. Thus, the phase locked loop circuit which maintains quick synchronization and the stable steady state is constituted. |
