PHASE LOCKED LOOP WITH LOW POWER FEEDBACK PATH AND OPERATIONMETHOD

摘要

PROBLEM TO BE SOLVED: To attain the reduction of power consumption while keeping a lock state in a phase locked loop(PLL). SOLUTION: A PLL 10 has 124th and 228th feedback paths for matching the phase and frequency of a generated clock signal with an input reference clock signal. Two feedback paths are delayed and matched so that both the paths can be used for keeping 'lock of PLL'. However, power consumption on the 1st path is remarkably less than that on the 2nd route. A control circuit 22 selects which path is to be fed back through a multiplexer and disables the 2nd path when the route is not required.